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IS31FL3216 integrated silicon solution, inc. ? www.issi.com 1 rev.a, 12/27/2011 16 channels led driver january 2012 general description the IS31FL3216 is a fun light led controller with an audio modulation mode. it can store data of 8 frames with internal ram to play small animations automatically. IS31FL3216 can sample the input signal to modulate the intensity of leds, or control 8 frames playing by internal adc block. the led current of each channel can be set in 256 steps by adjusting the pwm duty cycle through an i2c interface. 8 channels can be used as gpio ports. IS31FL3216 is available in qfn-28 (4mm 4mm). it operates from 2.7v to 5.5v over the temperature range of -40c to +85c. applications ? mobile phones and other hand-held devices for led display ? led in home appliances features ? 2.7v to 5.5v supply ? i2c interface, automatic address increment function ? internal ram ? modulate led brightness with 256 steps pwm ? each channel can be controlled independently ? auto frame play mode with 8 frames ? 8 frames memory for animations ? audio frame mode with 8 frames ? 8 of 16 outputs not used as led drivers can be used as gpio ports ? 8 levels of maximum intensity control ? 8kv hbm esd ? over-temperature protection ? -40c to +85c temperature range ? qfn-28 (4mm 4mm) package typical application circuit figure 1 typical application circuit note: the ic should be placed far away from the mobile antenna in order to prevent the emi.
IS31FL3216 integrated silicon solution, inc. ? www.issi.com 2 rev.a, 12/27/2011 figure 2 typical application circuit (cascade mode)
IS31FL3216 integrated silicon solution, inc. ? www.issi.com 3 rev.a, 12/27/2011 pin configuration package pin configuration (top view) qfn-28 pin description no. pin description 1 clk clock for chip cascade. 2 in audio signal input. 3 ~ 6 out1 ~ out4 output channel for leds. 7,16 gnd ground. 8 ~ 15 out5 ~ out12 output channel. 17 ~ 20 out13 ~ out16 output channel. 21 intb interrupt output, active low. 22 sdb shutdown, pull to gnd in the shutdown mode. 23 scl serial clock input. 24 sda serial data input. 25 ad i2c address pin. 26 vcc power supply. 27 c_filt filter capacitor for audio control. 28 r_ext external resistor to regulate the output current. thermal pad connect to gnd. copyright ? ? ? 2011 ? integrated ? silicon ? solution, ? inc. ? all ? rights ? reserved. ? issi ? reserves ? the ? right ? to ? make ? changes ? to ? this ? specification ? and ? its ? products at ? any ? time ? without ? notice. ? issi ? assumes ? no ? liability ? arising ? out ? of ? the ? application ? or ? use ? of ? any ? information, ? products ? or ? services ? described ? herein. ? customers ? are ? advised ? to ? obtain ? the ? latest ? version ? of ? this ? device ? specification ? before ? relying ? on ? any ? published ? information ? and ? before ? placing ? orders ? for ? products. ? integrated ? silicon ? solution, ? inc. ? does ? not ? recommend ? the ? use ? of ? any ? of ? its ? products ? in ? life ? support ? applications ? where ? the ? failure ? or ? malfunction ? of ? the ? product ? can ? reasonably ? be ? expected ? to ? cause ? failure ? of ? the ? life ? support ? system ? or ? to ? significantly ? affect ? its ? safety ? or ? effectiveness. ? products ? are ? not ? authorized ? for ? use ? in ? such ? applications ? unless ? integrated ? silicon ? solution, ? inc. ? receives ? written ? assurance ? to ? its ? satisfaction, ? that: ? a.) ? the ? risk ? of ? injury ? or ? damage ? has ? been ? minimized; ? b.) ? the ? user ? assume ? all ? such ? risks; ? and ? c.) ? potential ? liability ? of ? integrated ? silicon ? solution, ? inc ? is ? adequately ? protected ? under ? the ? circumstances
IS31FL3216 integrated silicon solution, inc. ? www.issi.com 4 rev.a, 12/27/2011 ordering information industrial range: -40c to +85c order part no. package qty/reel IS31FL3216-qfls2-tr qfn-28, lead-free 2500
IS31FL3216 integrated silicon solution, inc. ? www.issi.com 5 rev.a, 12/27/2011 absolute maximum ratings supply voltage, v cc - 0.3v ~ +6.0v voltage at any input pin - 0.3v ~ v cc +0.3v current in gnd terminal 1a maximum j unction temperature, t jmax 150c storage temperature range, t stg - 65c ~ +150c operating temperature range, t a ? 40c ~ +85c esd (hbm) 8kv note: stresses beyond those listed under ?absolute maximum ratings? may cause permanent damage to the device. these are stress rating s only and functional operation of the device at these or any other condition beyond those indicated in the operational sections of the sp ecifications is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. electrical characteristics t a = 25c, v cc = 2.7v ~ 5.5v, unless otherwise noted. typical values are t a = 25c, v cc = 3.6v. symbol parameter condition min. typ. max. unit v cc supply voltage 2.7 5.5 v i cc quiescent power supply current v sdb = v cc 5.2 ma i sd shutdown current v sdb = 0v or software shutdown 1 a i out average output current pwm control mode, v ds = 0.6v pwm duty cycle = 0xff 20 (note 1) ma audio frame mode, v ds = 0.6v v in = 3vp-p, 1khz square wave audio gain = 0db 20 (note 1) v hr current sink headroom voltage (when use as gpio output ports) i out = 20ma 400 mv logic electrical characteristi cs (sdb, sda, scl, ad, intb) v il logic ?0? input voltage v cc = 2.7v 0.4 v v ih logic ?1? input voltage v cc = 5.5v 1.4 v i il logic ?0? input current v in = 0v 5 (note 2,3) na i ih logic ?1? input current v in = v cc 5 (note 2,3) na
IS31FL3216 integrated silicon solution, inc. ? www.issi.com 6 rev.a, 12/27/2011 digital input switching characteristics (note 3) symbol parameter condition min. typ. max. unit f scl serial-clock frequency 400 khz t buf bus free time between a stop and a start condition 1.3 s t hd, sta hold time (repeated) start condition 0.6 s t su, sta repeated start condition setup time 0.6 s t su, sto stop condition setup time 0.6 s t hd, dat data hold time 0.9 s t su, dat data setup time 100 ns t low scl clock low period 1.3 s t high scl clock high period 0.7 s t r rise time of both sda and scl signals, receiving (note 4) 20+0.1cb 300 ns t f fall time of both sda and scl signals, receiving (note 4) 20+0.1cb 300 ns note 1: the average output current of each channel is iout. note 2: all leds are on. note 3: guaranteed by design. note 4: cb = total capacitance of one bus line in pf. isink 6ma. tr and tf measured between 0.3 v cc and 0.7 v cc .
IS31FL3216 integrated silicon solution, inc. ? www.issi.com 7 rev.a, 12/27/2011 detailed description i2c interface the IS31FL3216 uses a serial bus, which conforms to the i2c protocol, to control the chip?s functions with two wires: scl and sda. the IS31FL3216 has a 7-bit slave address (a7:a1), followed by the r/w bit, a0. set a0 to ?0? for a write command and set a0 to ?1? for a read command. the value of bits a1 and a2 are decided by the connection of the ad pin. the complete slave address is: table 1 slave address bit a7:a3 a2:a1 a0 value 11101 ad 1/0 ad connected to gnd, ad = 00; ad connected to vcc, ad = 11; ad connected to scl, ad = 01; ad connected to sda, ad = 10; the scl line is uni-directional. the sda line is bi-directional (open-collector) with a pull-up resistor (typically 4.7k ? ). the maximum clock frequency specified by the i2c standard is 400khz. in this discussion, the master is the microcontroller and the slave is the IS31FL3216. the timing diagram for the i2c is shown in figure 5. the sda is latched in on the stable high level of the scl . when there is no interface activity, the sda line should be held high. the ?start? signal is generated by lowering the sda signal while the scl signal is high. the start signal will alert all devices attached to the i2c bus to check the incoming address against their own chip address. the 8-bit chip address is sent next, most significant bit first. each address bit must be stable while the scl level is high. after the last bit of the chip address is sent, the master checks for the IS31FL3216?s acknowledge. the master releases the sda line high (through a pull-up resistor). then the master sends an scl pulse. if the IS31FL3216 has received the address correctly, then it holds the sda line low during the scl pulse. if the sda line is not low, then the master should send a ?stop? signal (discussed later) and abort the transfer. following acknowledge of IS31FL3216, the register address byte is sent, most significant bit first. IS31FL3216 must generate another acknowledge indicating that the register address has been received. then 8-bit of data byte are sent next, most significant bit first. each data bit should be valid while the scl level is stable high. after the data byte is sent, the IS31FL3216 must generate another acknowledge to indicate that the data was received. the ?stop? signal ends the transfer. to signal ?stop?, the sda signal goes high while the scl signal is high. address auto increment to write multiple bytes of data into IS31FL3216, load the address of the data register that the first data byte is intended for. during the IS31FL3216 acknowledge of receiving the data byte, the internal address pointer will increment by one. the next data byte sent to IS31FL3216 will be placed in the new address, and so on. the auto increment of the address will continue as long as data continues to be written to IS31FL3216 (figure 6). reading port registers to read the device data, the bus master must first send the IS31FL3216 address with the r/w ____ bit set to ?0?, followed by the command byte, which determines which register is accessed. after a restart, the bus master must then send the IS31FL3216 address with the r/w ____ bit set to ?1?. data from the register defined by the command byte is then sent from the IS31FL3216 to the master (figure 7). figure 3 interface timing
IS31FL3216 integrated silicon solution, inc. ? www.issi.com 8 rev.a, 12/27/2011 figure 4 bit transfer figure 5 writing to IS31FL3216(typical) figure 6 writing to IS31FL3216(automatic address increment) figure 7 reading from IS31FL3216
IS31FL3216 integrated silicon solution, inc. ? www.issi.com 9 rev.a, 12/27/2011 register definition table 2 register function address name function ta bl e r/w default 00h configuration register set the operating mode of IS31FL3216 3 w 1000 0000 01h led control register out9~out16 enable bit 4 w 1111 1111 02h out1~out8 enable bit 5 w 03h lighting effect register set the output current and the audio gain 6 w 0000 0000 04h channel configuration register set the operating mode of out9~out16 7 w 05h gpio configuration register set the operating mode of out9~out16 as the gpio port 8 w 06h output port register set the logic level of out9~out16 as the output port 9 w 07h interrupt control register set the interrupt function of out9~out16 10 w 08h state register store the state of out9~out16 as the input port 11 r xxxx xxxx 09h adc sample rate register set the adc sample rate of the input signal 12 w 0000 0000 10h~1fh pwm register set the pwm duty cycle data 13 w 20h~afh frame register store the data of 8 frames 14 w - b0h update register load pwm register data - w xxxx xxxx b6h frame delay register set the delay time between each frame 15 w 0000 0000 b7h frame start register set the start frame in auto frame play mode 16 w table 3 00h configuration register bit d7 d6:d5 d4 d3:d0 name ssd mode ae - default 1 00 0 0000 the configuration register sets the operating mode of IS31FL3216. ssd software shutdown enable 0 software shutdown mode 1 normal operation mode operation mode selection 00 pwm control mode 01 auto frame play mode 10 audio frame mode ae audio modulated enable 0 output current is set by register 1 output current is modulated by audio signal table 4 01h led control register(out9~out16) bit d7:d0 name out16:out9 default 1111 1111 table 5 02h led control register(out1~out8) bit d7:d0 name out8:out1 default 1111 1111 the led control registers store the on or off state of each channel. outx led state 0 led off 1 led on
IS31FL3216 integrated silicon solution, inc. ? www.issi.com 10 rev.a, 12/27/2011 table 6 03h lighting effect register bit d7 d6:d4 d3 d2:d0 name cm cs agce ags default 0 000 0 000 the lighting effect register sets the output current and the audio gain. cm chip cascade mode 0 master mode 1 slave mode cs output current selection 000 20ma 001 15ma 010 10ma 011 5ma 100 40ma 101 35ma 110 30ma 111 25ma agce agc enable 0 enable 1 disable ags audio gain selection 000 0db 001 3db 010 6db 011 9db 100 12db 101 15db 110 18db 111 21db table 7 04h channel configuration register (out9~out16) bit d7:d0 name out16:out9 default 0000 0000 configure the operating mode of out9~out16. if any port is set as gpio, the lighting effect register will be unavailable for the port. outx channel configuration 0 led output 1 gpio port table 8 05h gpio configuration register (out9~out16) bit d7:d0 name out16:out9 default 0000 0000 set the state of out9~out16 as the gpio port. outx gpio configuration 0 output port 1 input port table 9 06h output configuration register (out9~out16) bit d7:d0 name out16:out9 default 1111 1111 set the logic level of out9~out16 as the output port. outx output state 0 output low 1 output high table 10 07h interrupt control register (out9~out16) bit d7:d0 name out16:out9 default 0000 0000 set the interrupt function of out9~out16 as the input port. outx interrupt function enable 0 enable 1 disable table 11 08h state register (out9~out16) bit d7:d0 name out16:out9 default xxxx xxxx store the input state of out9~out16 as the input port (write only). the intb pin will be pulled high until the mcu reads the data of state register.
IS31FL3216 integrated silicon solution, inc. ? www.issi.com 11 rev.a, 12/27/2011 table 12 09h adc sample rate register bit d7:d0 name sr default 0000 0000 the value of adc sample rate register decides the sample rate of adc for audio frame mode. the sample rate could be computed using the formula (1): ? ? ? ? 7 0 2 ] [ / 625 . 15 sr n n n d khz (1) where ?n? indicates the bit lo cation in the respective adc sample rate register. for example: d7:d0 = 10110100 sr = 15.625khz/(2 2 +2 4 +2 5 +2 7 ) = 105hz table 13 10h~1fh pwm register (out16~out1) bit d7:d0 name pwm default 0000 0000 the pwm registers adjusts led luminous intensity in 256 steps. the value of a channel?s pwm register decides the average output current for each output, out1~out16. the average output current may be computed using the formula (2): ? ? ? ? ? 7 0 out 2 ] [ 256 i n n max n d i (2) where ?n? indicates the bit lo cation in the respective pwm registers. for example: d7:d0 = 10110101 i out = i max (2 0 +2 2 +2 4 +2 5 +2 7 )/256 i max is set by the lighting effect register (03h). table 14 20h~afh frame register address list led control register pwm register frame 1 20h ~ 21h 22h ~ 31h frame 2 32h ~ 33h 34h ~ 43h frame 3 44h ~ 45h 46h ~ 55h frame 4 56h ~ 57h 58h ~ 67h frame 5 68h ~ 69h 6ah ~ 79h frame 6 7ah ~ 7bh 7ch ~ 8bh frame 7 8ch ~ 8dh 8eh ~ 9dh frame 8 9eh ~ 9fh a0h ~ afh frame registers store the data of 8 frames. each frame is controlled by two led control registers and sixteen pwm registers. the detail about the led control register is shown in table 4, 5 and the pwm register is shown in table 13. b0h update register the data sent to the pwm register will be stored in temporary registers. a write operation of any 8-bit value to the update register is required to update the registers. table 15 b6h frame delay register bit d7:d5 d4:d0 name fdt - default 000 00000 set the delay time between each frame in auto frame play mode. fdt frame delay time 000 32ms 001 64ms 010 128ms 011 256ms 100 512ms 101 1.024s 110 2.048s 111 4.096s table 16 b7h frame start register bit d7:d5 d4:d0 name fs - default 000 00000 set the start frame in auto frame play mode. fs frame start 000 frame 1 001 frame 2 010 frame 3 011 frame 4 100 frame 5 101 frame 6 110 frame 7 111 frame 8 for example, if fs bit sets to ?011?, it plays from the fourth frame to the eighth frame then cycled back to the first frame.
IS31FL3216 integrated silicon solution, inc. ? www.issi.com 12 rev.a, 12/27/2011 typical application pwm control by setting the mode bit of the configuration register (00h) to ?00?, IS31FL3216 operates in pwm control mode. the led brightness of 16 channels can be modulated with 256 steps by pwm registers. for example, if the data in pwm register is ?0000 0100?, then the pwm is the fourth step. writing new data continuously to the registers can modulate the brightness of the leds to achieve a breathing effect. gamma correction in order to perform a better visual led breathing effect we recommend using a gamma corrected pwm value to set the led intensity. this results in a reduced number of steps for the led intensity setting, but causes the change in intensity to appear more linear to the human eye. gamma correction, also known as gamma compression or encoding, is used to encode linear luminance to match the non-linear characteristics of display. since the IS31FL3216 can modulate the brightness of the leds with 256 steps, a gamma correction function can be applied when computing each subsequent led intensity setting such that the changes in brightness matches the human eye's brightness curve. table 17 32 gamma steps with 256 pwm steps c(0) c(1) c(2) c(3) c(4) c(5) c(6) c(7) 0 1 2 4 6 10 13 18 c(8) c(9) c(10) c(11) c(12) c(13) c(14) c(15) 22 28 33 39 46 53 61 69 c(16) c(17) c(18) c(19) c(20) c(21) c(22) c(23) 78 86 96 106 116 126 138 149 c(24) c(25) c(26) c(27) c(28) c(29) c(30) c(31) 161 173 186 199 212 226 240 255 0 32 64 96 128 160 192 224 256 0 4 8 121620242832 pwm data intensity steps figure 8 gamma correction(32 steps) choosing more gamma steps provides for a more continuous looking breathing effect. this is useful for very long breathing cycles. the recommended configuration is defined by the breath cycle t. when t=1s, choose 32 gamma steps, when t=2s, choose 64 gamma steps. the user must decide the final number of gamma steps not only by the led itself, but also based on the visual performance of the finished product. table 18 64 gamma steps with 256 pwm steps c(0) c(1) c(2) c(3) c(4) c(5) c(6) c(7) 0 1 2 3 4 5 6 7 c(8) c(9) c(10) c(11) c(12) c(13) c(14) c(15) 8 10 12 14 16 18 20 22 c(16) c(17) c(18) c(19) c(20) c(21) c(22) c(23) 24 26 29 32 35 38 41 44 c(24) c(25) c(26) c(27) c(28) c(29) c(30) c(31) 47 50 53 57 61 65 69 73 c(32) c(33) c(34) c(35) c(36) c(37) c(38) c(39) 77 81 85 89 94 99 104 109 c(40) c(41) c(42) c(43) c(44) c(45) c(46) c(47) 114 119 124 129 134 140 146 152 c(48) c(49) c(50) c(51) c(52) c(53) c(54) c(55) 158 164 170 176 182 188 195 202 c(56) c(57) c(58) c(59) c(60) c(61) c(62) c(63) 209 216 223 230 237 244 251 255 0 32 64 96 128 160 192 224 256 0 8 16 24 32 40 48 56 64 pwm data intensity steps figure 9 gamma correction(64 steps) note, the data of 32 gamma steps is the standard value and the data of 64 gamma steps is the recommended value.
IS31FL3216 integrated silicon solution, inc. ? www.issi.com 13 rev.a, 12/27/2011 auto frame play mode by setting the mode bit of the configuration register (00h) to ?01?, the IS31FL3216 operates in auto frame play mode. it stores data of 8 frames and automatically plays in order. customers can configure the delay time between each two frames and the first playing frame by setting the frame delay register (b6h) and the frame start register (b7h). audio frame mode by setting the mode bit of the configuration register (00h) to ?10?, the IS31FL3216 operates in audio frame mode. it stores data of 8 frames and the 8 frames playing follow the input signal. 09h register is used to set the adc sample rate for the input signal to control frames playing. it plays the first frame when the value is the smallest and plays the eighth frame when the value is the biggest (see table 14). audio modulated mode and gain setting by setting the ae bit of the c onfiguration register to ?1?, IS31FL3216 operates in audio modulated mode. the intensity of leds is adjusted by the input signal. the audio input gain can be set by the lighting effect register (03h). channel mode setting IS31FL3216 has 16 channels for leds output. out9~out16 also can be set as gpio ports. by setting the outx bit of the channel register to ?1?, the corresponding channel will be used as gpio port. when the outx is set to ?0?, the corresponding channel will be used as led output. cascade for synchronization of chips operating in the cascade mode can make two chips synchronize. by setting the cm bit of the lighting effect register (03h) to ?0?, IS31FL3216 operates as a master. the clk pin offers the output clock signal. when the cm bit sets to ?1?, IS31FL3216 operates as a slave. the clk pin as a clock input pin. if there is only one chip to use, setting cm bit to ?0? and the clk pin should be floating. interrupt function when out9~out16 configure as input port and the interrupt function enabled, the intb pin is available. if any input port of out9~out16 has state changing, the intb pin will be pulled low. the mcu can get the information via reading the state register (08h). the intb will be back to high until the mcu reading the state register (08h). shutdown mode shutdown mode can either be used as a means of reducing power. during shutdown mode all registers retain their data and out9~out16 still can be available as gpio port. software shutdown by setting ssd bit of the configuration register (00h) to ?0?, the IS31FL3216 will operate in software shutdown mode, wherein they consume only 1 a (typ.) current. when the IS31FL3216 is in software shutdown mode, all current sources are switched off. hardware shutdown the chip enters hardware shutdown mode when the sdb pin is pulled low.
IS31FL3216 integrated silicon solution, inc. ? www.issi.com 14 rev.a, 12/27/2011 classification reflow profiles profile feature pb-free assembly preheat & soak temperature min (tsmin) temperature max (tsmax) time (tsmin to tsmax) (ts) 150c 200c 60-120 seconds average ramp-up rate (tsmax to tp) 3c/second max. liquidous temperature (tl) time at liquidous (tl) 217c 60-150 seconds peak package body temperature (tp)* max 260c time (tp)** within 5c of the specified classification temperature (tc) max 30 seconds average ramp-down rate (tp to tsmax) 6c/second max. time 25c to peak temperature 8 minutes max. figure 10 classification profile
IS31FL3216 integrated silicon solution, inc. ? www.issi.com 15 rev.a, 12/27/2011 tape and reel information
IS31FL3216 integrated silicon solution, inc. ? www.issi.com 16 rev.a, 12/27/2011 package information qfn-28 note: all dimensions in millimeters unless otherwise stated.

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